1. Field of the Invention
The present invention relates to ultra-thin, high performance, and extreme high-density electronic packages. More particularly, the present invention uses chip thinning, adhesive bonding, and laminated microelectronic interconnect technology to provide a circuit package with extremely low thickness dimensions. These thin circuit packages can be stacked vertically to create a three dimensional electronic package with the highest possible functionality per volume.
2. Description of Related Art
Chip thinning has been available in rudimentary form for many years. Backside grinding to the range of 100-200 .mu.m silicon thickness is commonly employed where high heat transfer or low profiles are required. The minimum thickness is 100 .mu.m in order to avoid chip damage. For silicon thickness of 50 .mu.m and below the chip shows some flexibility that increases as the thickness decreases.
Adhesive flip-chip bonding has been used with success in applications such as chip-on-glass for flat panel displays, chip-on-flex, and for high-end multi-chip modules. See, for example, Zenner, Proceedings International Conference on Electronic Assembly, IPC Northbrook, Ill., May, 1996, Vol. 2, IPC-TP-1111 pp. 1-14. The bond-line between pads using adhesive flip-chip can be as low as several microns. For bumped chip bonds the height of the gold bump largely determines the bond-line thickness. Added particles determine the bond-line thickness with unbumped chips and these are usually in the range of 5-10 microns. Bumped chip bonding methods involve a relatively simple task of compressing the bump into the circuit pad to make a reliable connection. Reliable bonding methods for unbumped thin chips demand greater care to insure that the conductive particles are indeed trapped between the contact pads and that excess particles do not bridge to a nearby pad location.
Laminated microelectronic interconnect flex circuitry is designed to enable multiple layers of 25 .mu.m thick flex circuitry to be used to prepare densely routed, flexible circuits with actual thickness of about 50 .mu.m/layer. See, for example U.S. Pat. No. 5,601,678 to Gerber et al. Interlayer vias are included which have a total diameter of only 4 mils (100 .mu.m) with capture pads having 6 mils (150 .mu.m) diameter. Typical vias prepared by drilling and plating require capture pad diameter of at least 16 mils (400 .mu.m). Thus this laminated flex can enable routing much finer than conventional laminate circuits. Flip-chip attachment will generally require very fine pitch at the inner lead region due to the fine pad pitch (about 200 .mu.m) and high pad count found on many integrated circuit chips. Flip-chip bonding of multiple chips on laminate flex is only possible because the lines can escape through to the lower routing layer owing to this small via size.
Commonly used techniques for flip-chip interconnect required bonding with reflowed solder ball bumps at each bonding site on the chip. Typically, these solder ball bumps have a stand-off height of more than 100 .mu.m. Another common attachment technique for bare integrated circuit chips is wire bonding of face-up surface mounted chips. The wire loops up and out from the pad give an effective height again on the order of 100 .mu.m. These wires are usually protected by adding glob-top curable pastes that add still more height to each chip bond. While both of these bare chip bonding methods could conceivably be performed using thin chips (501 .mu.m or less silicon thickness) they remain handicapped by the stand-off limits of greater than 100 .mu.m in height that will prevent the production of an ultra-thin package.